The invention relates to flip-flop arrangement for halving a frequency of a signal received on an input terminal. A flip-flop arrangement of this kind is known from IEEE Electron Device Letters Vol. EDL-4, No. 10, October 1983, pp. 377-379. The known arrangement comprises five two-inputs NOR-gates and one three-inputs NOR-gate, each gate comprising a load-transistor and two or three driver transistors. General problems that designers of VLSI circuitry have to cope with relate to the reduction of the number of components in a circuit for performing a predetermined function and to the reduction of power consumption, that, among others, is associated with the number of components and the number of current conduction paths between the supply terminals. These problems should preferably be solved without degrading the performance and the dynamic characteristics of the circuitry.